The present invention relates to a semiconductor device, and especially to technology which can be utilized suitably in a semiconductor device provided with an output circuit of a differential signal, for example.
In an output circuit of a differential signal, it is important to suppress a variation of a common voltage in order to realize a high speed and long-distance transmission. For example, when a pre-emphasis circuit or a de-emphasis circuit is provided, it is necessary to make the circuit affect only the amplitude of an output signal, without affecting the common voltage.
Published Japanese Unexamined Patent Application No. 2011-71798 (Patent Literature 1) discloses technology which suppresses a variation of a common voltage arising from a pattern of signal data, in an output circuit provided with a de-emphasis function. Specifically, by providing a detector for detecting a data pattern to be transmitted, a current of the output circuit is compensated at the time of the appearance of a specific transmitting data pattern and its reverse pattern.
In an output circuit disclosed by Published Japanese Unexamined Patent Application No. 2011-142382 (Patent Literature 2), when applying de-emphasis to an output signal on the high potential side of differential output signals, a current flowing through a transistor which supplies the de-emphasis current concerned is reduced.
An output circuit disclosed by Published Japanese Unexamined Patent Application No. 2010-283453 (Patent Literature 3) is provided with a circuit which reinforces the pre-emphasis operation of a differential output signal at the time of pre-emphasis, and which switches off a path having performed the pre-emphasis of the differential output signal and switches on a current path between a high-potential-side power source and a low-potential-side power source at the time of de-emphasis.
Furthermore, there are other patent literatures cited below as technology relevant to the technology described above. Published Japanese Unexamined Patent Application No. 2007-60072 (Patent Literature 4) discloses an output circuit provided with a mode for performing an amplitude marginal test with a simple configuration, without influencing a normal operation mode for performing de-emphasis. Published Japanese Unexamined Patent Application No. 2009-171562 (Patent Literature 5) discloses technology in which a comparator circuit is employed as a common voltage adjusting circuit.    (Patent Literature 1) Published Japanese Unexamined Patent Application No. 2011-71798    (Patent Literature 2) Published Japanese Unexamined Patent Application No. 2011-142382    (Patent Literature 3) Published Japanese Unexamined Patent Application No. 2010-283453    (Patent Literature 4) Published Japanese Unexamined Patent Application No. 2007-60072    (Patent Literature 5) Published Japanese Unexamined Patent Application No. 2009-171562